Add-On Programs

M.Tech – VLSI Design

Chip Design — Where Every Transistor Counts

The M.Tech in VLSI Design at BRIL focuses on semiconductor technology, chip design, and embedded hardware systems. With India's semiconductor mission gaining momentum and global chip companies expanding their design centres in Hyderabad and Bengaluru, VLSI engineers with strong hands-on skills are in genuine demand.

Add-on programmes provide exposure to industry-standard EDA tools, advanced design methodologies, and the full chip design flow — from RTL to GDSII — giving students a clear advantage in the semiconductor job market.

M.Tech VLSI Add-On

Add-On Programmes

CMOS VLSI Design & Fabrication Concepts

The physical foundation of chip design — understanding how transistors are built and how they behave at scale.

MOS Transistor Physics & Characteristics
CMOS Logic Gate Design & Sizing
Semiconductor Fabrication Process Overview
Technology Scaling & Short Channel Effects
SPICE Simulation & Circuit Characterisation

FPGA Design & Verification

FPGAs are the prototyping platform of choice for chip designers — and increasingly used in production systems for defence, telecom, and AI acceleration.

FPGA Architecture (Xilinx / Intel Altera)
RTL Design & Synthesis for FPGA
Timing Constraints & Static Timing Analysis
IP Core Integration & AXI Bus Protocols
Hardware-Software Co-Design Basics

ASIC Design Flow & Implementation

The complete RTL-to-GDSII flow — the core skill set for any VLSI design engineer working in a semiconductor company.

RTL Design & Functional Verification
Logic Synthesis (Synopsys Design Compiler)
Formal Verification & Equivalence Checking
DFT & Scan Chain Insertion
Sign-Off Checks (LVS, DRC, ERC)

HDL Programming (Verilog / VHDL)

Hardware description languages are the primary tool of the chip designer — fluency in both Verilog and VHDL is expected in the industry.

Verilog RTL Coding & Testbench Writing
VHDL Design & Simulation
SystemVerilog for Verification
UVM (Universal Verification Methodology) Basics
Functional Coverage & Assertions

Physical Design & Layout Techniques

The back-end of chip design — translating a synthesised netlist into a manufacturable layout that meets timing, power, and area targets.

Floorplanning & Power Planning
Placement & Clock Tree Synthesis (CTS)
Routing & Signal Integrity
IR Drop & Electromigration Analysis
GDSII Generation & Tape-Out Preparation

Low Power VLSI Design

Power consumption is one of the biggest constraints in modern chip design — from mobile SoCs to data centre processors.

Dynamic & Static Power Analysis
Clock Gating & Power Gating Techniques
Multi-Voltage Design & Level Shifters
UPF (Unified Power Format) Implementation
Power-Aware Synthesis & Optimisation

Technical Exposure

Hands-on training with industry-standard EDA tools including Cadence, Synopsys, and Mentor Graphics platforms

Design simulation and verification practices using real-world chip design scenarios and industry-grade testbenches

Industry-oriented mini and major projects covering the complete ASIC or FPGA design flow from specification to sign-off

Placement Impact

Target Roles

RTL Design Engineer, Physical Design Engineer, Verification Engineer, FPGA Engineer, DFT Engineer, Low Power Design Engineer

Recruiting Sectors

Semiconductor Companies, Fabless Design Houses, EDA Tool Vendors, Defence Electronics, Telecom Chip Makers, Automotive IC Design

Certifications Supported

Cadence Certified Designer, Xilinx FPGA Developer, Synopsys Training Certificate, VLSI Expert Certification

Outcome

Students gain specialised expertise in chip design and hardware systems — preparing them for careers in semiconductor industries, embedded systems, and core electronics sectors at a time when India's chip design ecosystem is expanding rapidly.